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INTEGRATED CIRCUITS
DATA SHEET
TDA8798 Dual 8-bit, 100 Msps A/D converter with DPGA
Objective specification Supersedes data of 1998 Apr 15 File under Integrated Circuits, IC02 1999 Sep 16
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with DPGA
FEATURES * Dual 8-bit Analog-to-Digital Converter (ADC) * Sampling rate up to 100 million samples per second (Msps) * Dual 34 dBV 6-bit Digitally Programmable Gain Amplifier (DPGA) with optional power-off * Optional external equalization filter with capacitive coupling between DPGA and ADC * Serial Interface (SI) for DPGA gain control using either parallel load mode or count-up/count-down mode * 3.3 V TTL/CMOS compatible I/O * Differential or single-ended TTL/CMOS clock interface * AC or DC coupling for DPGA inputs. QUICK REFERENCE DATA SYMBOL VDDA VDDD VDDO IDDA IDDD IDDO INL PARAMETER analog supply voltage digital supply voltage output stage supply voltage analog supply current digital supply current output stage supply current DC integral non-linearity from IC analog input to digital output; ramp input; fCLK = 100 MHz with DPGA at G(min) without DPGA DNL DC differential non-linearity from IC analog input to digital output; ramp input; fCLK = 100 MHz with DPGA at G(min) without DPGA Vn(o)(rms) B(-3dB)(ADC) f(sample)(max) Ptot output referred noise (RMS value) ADC -3 dB analogue bandwidth maximum sampling rate total power dissipation with DPGAEN LOW with DPGAEN HIGH DPGA at G(max); Zi = 50 ; noise bandwidth = 15 MHz at Vi(dif)(FS) at Vi(dif)(max) - - - - 30 100 - - 0.5 0.5 tbf 120 tbf - 460 tbf - - 3.0 1.0 with DPGAEN LOW with DPGAEN HIGH CONDITIONS MIN. 3.15 3.0 2.7 - - - - TYP. 3.3 3.3 3.3 106 tbf 30 3 APPLICATIONS
TDA8798
* High-dynamic range acquisition front-ends * Digital data storage read channels. GENERAL DESCRIPTION The TDA8798 is a dual 8-bit ADC with DPGA. The 100 Msps maximum sampling rate and 34 dBV DPGA gain range optimizes the ADC for high dynamic range applications.
MAX. 3.45 3.6 3.6 - - - -
UNIT V V V mA mA mA mA
tbf tbf
LSB LSB
tbf tbf 2 - - - 500 tbf
LSB LSB mVrms MHz MHz Msps mW mW
B(-3dB)(DPGA) DPGA -3 dB bandwidth
1999 Sep 16
2
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with DPGA
ORDERING INFORMATION TYPE NUMBER TDA8798HL PACKAGE NAME LQFP64 DESCRIPTION plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
TDA8798
VERSION SOT314-2
BLOCK DIAGRAM
handbook, full pagewidth
to DPGA2 to DPGA2N
OPTIONAL EXTERNAL FILTER 2 DPGA2 BUF2N BUF2 63 64
to BUF2 to BUF2N Voref2 TEST 62 54 55 TE SR 52 VSSA4 OE
DPGAC2 3
DPGA2N 2 1
VDDA4 60 61 51 58 CLK2 CLK2N digital output 2 B0 to B7 Vref2
REGULATOR analog VIN2N input 2 VIN2 VDDA2 VSSA2 VSSD1 VDDD1 DPGAEN VDDD2 VSSD2 VSSA1 VDDA1 analog input 1 VIN1 VIN1N 6 A 7 5 8 24 25 53 56 57 9 12 10 A 11 DPGA1 BUFFER D 6 ADC1 SERIAL INTERFACE 6 DPGA2 BUFFER D ADC2
59 41 to 48
4
TDA8798
27 29 26 28 30
SEN2 SCLK SMODE SDATA SEN1
13
Vref1 digital output 1 A0 to A7 CLK1 CLK1N
40 to 33
23 REGULATOR 14 DPGAC1 15 16 18 17 19 20 21 31 50 32 49
MGM863
22
DPGA1N
BUF1
VDDA3 Voref1
VDDO1
VSSO1 VSSO2
DPGA1 to DPGA1N to DPGA1
BUF1N
VSSA3
VDDO2
OPTIONAL EXTERNAL FILTER 1
to BUF1N to BUF1
Fig.1 Block diagram.
1999 Sep 16
3
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with DPGA
TDA8798
handbook, full pagewidth
Co(DPGA) IOUT Ro(DPGA)
DPGA(1) 10 H L
100 nF C
BUF(2) Ri(ADC) Ci(ADC)
R 1 k -IOUT Co(DPGA) Ro(DPGA) DPGAN(3) L 10 H Ri(ADC) BUFN(4) Ci(ADC)
C
100 nF
TDA8798
TDA8798
FCE267
External filtering may be used between DPGA and ADC to limit the noise bandwidth. 1 R 2 + R o ( DPGA ) The external filter has a low-pass cut-off frequency of f l ( -3dB ) ------ x ------------------------------------------ . 2 L 1 1 and a high-pass cut-off frequency of f h ( -3dB ) ------ x ----------------------------2 R i ( ADC ) x C Other types of filter may be used if DC biasing is correct.
.
(1) (2) (3) (4)
DPGA1/DPGA2 BUF1/BUF2 DPGA1N/DPGA2N BUF1N/BUF2N
Fig.2 External filter.
PINNING SYMBOL DPGA2N DPGA2 DPGAC2 Vref2 VDDA2 VIN2N VIN2 VSSA2 VSSA1 VIN1 VIN1N VDDA1 Vref1 DPGAC1 DPGA1 DPGA1N PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DPGA2 inverting output DPGA2 non-inverting output DPGA2 bandwidth limitation control ADC2 reference output DPGA2 analog supply voltage DPGA2 inverting input voltage DPGA2 non-inverting input voltage DPGA2 analog ground DPGA1 analog ground DPGA1 non-inverting input voltage DPGA1 inverting input voltage DPGA1 analog supply voltage ADC1 reference output DPGA1 bandwidth limitation control DPGA1 non-inverting output DPGA1 inverting output DESCRIPTION
1999 Sep 16
4
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with DPGA
SYMBOL BUF1 BUF1N Voref1 VDDA3 VSSA3 CLK1N CLK1 VSSD1 VDDD1 SMODE SEN2 SDATA SCLK SEN1 VDDO1 VSSO1 A7 A6 A5 A4 A3 A2 A1 A0 B0 B1 B2 B3 B4 B5 B6 B7 VSSO2 VDDO2 OE SR DPGAEN TEST TE VDDD2 VSSD2 1999 Sep 16 PIN 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 buffer1 non-inverting input buffer1 inverting input buffer1 common mode reference output ADC1 analog supply voltage 3 ADC1 analog ground 3 ADC1 inverting clock input ADC1 non-inverting clock input digital ground 1 digital supply voltage 1 serial interface mode input serial interface enable 2 (active low) serial interface data input serial interface clock input serial interface enable 1 (active low) output stage supply voltage 1 output stage ground 1 channel 1 output bit 7 (MSB) channel 1 output bit 6 channel 1 output bit 5 channel 1 output bit 4 channel 1 output bit 3 channel 1 output bit 2 channel 1 output bit 1 channel 1 output bit 0 (LSB) channel 2 output bit 0 (LSB) channel 2 output bit 1 channel 2 output bit 2 channel 2 output bit 3 channel 2 output bit 4 channel 2 output bit 5 channel 2 output bit 6 channel 2 output bit 7 (MSB) output stage ground 2 output stage supply voltage 2 digital output enable (active LOW) digital output bit slew-rate control DPGA enable (active LOW) test input (to be grounded) track-and-hold enable (active LOW) digital supply voltage 2 digital ground 2 5 DESCRIPTION
TDA8798
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with DPGA
SYMBOL CLK2 CLK2N VSSA4 VDDA4 Voref2 BUF2N BUF2 PIN 58 59 60 61 62 63 64 ADC2 non-inverting clock input ADC2 inverting clock input ADC2 analog ground 4 ADC2 analog supply voltage 4 buffer2 common mode reference output buffer2 inverting input buffer2 non-inverting input DESCRIPTION
TDA8798
53 DPGAEN
50 VDDO2
56 VDDD2
61 VDDA4
62 Voref2
64 BUF2
54 TEST
58 CLK2
handbook, full pagewidth
DPGA2N
1
49 VSSO2 48 B7 47 B6 46 B5 45 B4 44 B3 43 B2 42 B1 41 B0 40 A0 39 A1 38 A2 37 A3 36 A4 35 A5 34 A6 33 A7 VSSO1 32
63 BUF2N
57 VSSD2
60 VSSA4
59 CLK2N
DPGA2 2 DPGAC2 3 Vref2 4 VDDA2 5 VIN2N 6 VIN2 7 VSSA2 8 VSSA1 9 VIN1 10 VIN1N 11 VDDA1 12 Vref1 13 DPGAC1 14 DPGA1 15 DPGA1N 16 VDDA3 20 VSSA3 21 CLK1N 22 CLK1 23 VSSD1 24 VDDD1 25 SMODE 26 SEN2 27 SDATA 28 SCLK 29 SEN1 30 VDDO1 31 BUF1 17 BUF1N 18 Voref1 19
TDA8798HL
52 SR
55 TE
51 OE
MGM864
Fig.3 Pin configuration.
1999 Sep 16
6
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with DPGA
FUNCTIONAL DESCRIPTION The TDA8798 comprises two independent fully differential signal chains each having a DPGA and a high-speed ADC. A serial interface allows the gain of each DPGA to be controlled independently. To improve signal conditions, an AC-coupled external filter can be connected between a DPGA and ADC. The TDA8798 can be used as a dual 8-bit ADC without DPGA functionality, using less power. Digitally Programmable Gain Amplifier (DPGA) The gain of the differential DPGA is programmable from 0 to 34 dBV in 63 equal steps by a 6-bit word output in parallel from a gain control register in the SI. For all gain settings, the DPGA signal bandwidth exceeds 30 MHz. The settling time between gain changes can be adjusted by an external decoupling capacitor connected to DPGAC1 (pin 14) and/or DPGAC2 (pin 3). The analog input signals can be either AC or DC coupled. When used only as a dual 8-bit ADC, both DPGAs can be disabled to reduce power consumption. Analog-to-Digital Converter (ADC) The 8-bit ADC converts the differential analog input signal into a binary output format at a maximum conversion rate of 100 Msps. All digital input and output signals are TTL/CMOS compatible. The ADC clock signal can be from either a differential or a single-ended source; when single-ended, the unused clock input pin should be decoupled externally. The analog input to the ADC is AC coupled. When used only as a dual ADC, the ADC can be externally biased by regulator output Voref1 (pin 19) and/or Voref2 (pin 62) using series resistors of, for example, 50 , connected to the ADC buffer inputs providing a lower input impedance. This requires Voref1 and/or Voref2 to be decoupled to ground by a 10 nF capacitor. Vref1 (pin 13) and/or Vref2 (pin 4) provide a voltage corresponding to the bias of the ADC which can be used as a reference output to an external control circuit. Alternatively, an external control voltage can be applied to these pins to adjust the full-scale range of the ADC. Serial Interface (SI)
TDA8798
The SI allows the gain of each DPGA to be controlled independently using either a parallel load mode or a count-up/count-down mode. The gain control mode is selected by the state of SMODE. The operation of DPGA gain control is shown in Timing diagram, (see Fig.4). Parallel load mode This mode loads gain control data serially into a decoder in the SI. Each of the six bits are loaded on the rising edge of SCLK. After the load has completed, SEN goes inactive, loading the data in parallel to a gain control register in the SI, changing the gain of the DPGA. Count-up/count-down mode Count-up/count-down mode is selected when SMODE is in the opposite state to parallel load mode. This mode either increments or decrements the SI gain control register in one-bit steps when SEN and SCLK are both active; the state of SDATA determines the count direction (up or down). This allows the gain of the DPGA to be changed asynchronously and intermittently. ADC digital outputs Digital noise on the internal supply lines increases when the VDDO voltage increases, affecting the crosstalk between channels. This effect can be reduced by making SR (pin 52) HIGH, changing the slew-rate of the ADC digital outputs.
1999 Sep 16
7
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with DPGA
Table 1 Serial interface truth table; see notes 1 and 2 SCLK SEN1 1 SEN2 1 SDATA U
TDA8798
SMODE 0
ACTION WAIT SISR: SISR Di SISR: SISR 1 GCR1: GCR1 + 1 SISR: SISR 0 GCR1: GCR1 - 1 SISR: SISR 1 GCR2: GCR2 + 1 SISR: SISR 0 GCR2: GCR2 - 1 SISR: SISR 1 GCR1: GCR1 + 1 GCR2: GCR2 + 1
X,
0 0 0 0 0 0
1 0 0 1 1 0
1 1 1 0 0 0
Di 1 0 1 0 1
0
0
0
0
SISR: SISR 0 GCR1: GCR1 - 1 GCR2: GCR2 - 1
1
X,
X, X,
X, X, X,
U
WAIT SISR: SISR Di
1
Di
1
X, X, X, X,
U
GCR1: SISR
1
U
GCR2: SISR
1
U
GCR1: SISR GCR2: SISR
Notes 1. ` Di': shifting LSB and loading new LSB with value Di. 2. In count-up/count-down mode, the gain control register cannot be incremented above the maximum gain value of 63, or decremented below the minimum gain value of 0.
1999 Sep 16
8
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with DPGA
Table 2 Abbreviations DESCRIPTION DPGA1 gain control register value DPGA2 gain control register value Serial interface shift register value can be either logic state 0 or logic state 1 rising edge falling edge Table 6 U Di Table 3 can be either undefined logic state X rising edge or falling edge Data input TE truth table ADC TRACK-AND-HOLD track-and-hold enabled track enabled Gain Control GAIN CONTROL REGISTER VALUE 000000 000001 000010 ... ... ... 111110 111111 0.00 0.54 1.08 ... ... ... 33.46 34.00 Table 5 DPGAEN truth table DPGAEN 0 1 Table 4 SR truth table
TDA8798
SYMBOL GCR1 GCR2 SISR X
SR 0 1
ADC DIGITAL OUTPUT SLEW RATE maximum minimum
DPGA FUNCTIONALITY enabled disabled
GAIN (dBV)
TE 0 1
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDA VDDD VDDO VDDX PARAMETER analog supply voltage digital supply voltage output stage supply voltage supply voltage differences between VDDA and VDDD VDDO and VDDD VDDA and VDDO Vi(VIN) IO Tstg Tamb Tj input voltage range on VIN1 and VIN2 (pins 10 and 7) output current storage temperature ambient temperature junction temperature referenced to VSSA -1.0 -1.0 -1.0 -0.3 - -55 0 - +1.0 +1.0 +1.0 +7.0 10 +150 70 104 V V V V mA C C C CONDITIONS MIN. -0.3 -0.3 -0.3 MAX. +7.0 +7.0 +7.0 UNIT V V V
1999 Sep 16
9
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with DPGA
HANDLING
TDA8798
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 68 UNIT K/W
CHARACTERISTICS VDDA = V5 (or V12 or V20 or V61) to V8 (or V9 or V21 or V60) = 3.15 to 3.45 V; VDDD = V25 (or V56) to V24 (or V57) = 3.0 to 3.6 V; VDDO = V31 (or V50) to V32 (or V49) = 2.7 to 3.6 V; VSSA, VSSD and VSSO shorted together; VDDA to VDDD = -0.25 to +0.25 V; VDDD to VDDO = -0.25 to +0.90 V; VDDA to VDDO = -0.25 to +0.75 V; Tamb = 0 to 70 C; typical values measured at VDDA = VDDD = VDDO = 3.3 V and Tamb = 25 C; unless otherwise specified. SYMBOL Supplies VDDA VDDD VDDO IDDA IDDD IDDO analog supply voltage digital supply voltage output stage supply voltage analog supply current digital supply current output stage supply current fCLK = 100 MHz; ramp input DPGAEN LOW DPGAEN HIGH 3.15 3.0 2.7 - - - - 3.3 3.3 3.3 106 tbf 30 3 3.45 3.6 3.6 - - - - V V V mA mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Digital programmable gain amplifiers ANALOG INPUTS (VIN1, VIN1N, VIN2 AND VIN2N) Vi(dif)(max)(p-p) Vi(cm)(DPGA) Ii(DPGA) Ri(DPGA) Ci(DPGA) Vo(dif)(max)(p-p) Vo(cm)(DPGA) Ro(DPGA) Co(DPGA) maximum differential input voltage (peak-to-peak value) common mode input voltage input current input resistance input capacitance at Vi(cm)(DPGA) at G(min) at G(max) - - tbf - 1 - at G(min) at G(max) at Vo(cm)(DPGA) - - - - - 0.5 10 2.8 tbf - - 0.5 0.5 3.1 115 - - - tbf - - 5 - - - 160 5 V mV V A k pF
ANALOG OUTPUTS (DPGA1, DPGA1N, DPGA2 AND DPGA2N) maximum differential output voltage (peak-to-peak value) common mode output voltage output resistance output capacitance V V V pF
1999 Sep 16
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Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with DPGA
SYMBOL PARAMETER DPGA -3 dB bandwidth settling time group delay CONDITIONS MIN. TYP.
TDA8798
MAX. - -
UNIT
BANDWIDTH AND SETTLING B(-3dB)(DPGA) tst td(g) at Vi(dif)(max) full-scale transition 10% to 90% fi up to 15 MHz at G(min) at G(max) GAIN G(min) G(max) Gstep Gstep(L) G(m)(c-c) G/T G/VDD minimum gain setting maximum gain setting gain step size gain step size linearity (actual gain step/average - 1) channel-to-channel gain matching amplifier gain stability as a function of temperature amplifier gain stability as a function of power supply voltage at G(min) at G(max) at G(min) at G(max) at G(min) at G(max) tbf tbf - -0.75 - - - - - - 0 34 0.54 - tbf tbf 8 8 0.4 0.8 tbf tbf - dBV dBV dBV - - tbf tbf - - ps ps 30 40 tbf - MHz ns
+0.75 dBV - - tbf tbf tbf tbf dB dB mdB/C mdB/C dB/V dB/V
GAIN SWITCHING; TAMB = 25 C tst(G-G) tPD REJECTION PSRR CMRR power supply rejection ratio common mode rejection ratio DC to 15 MHz at G(min) 40 40 - - - - dB dB settling time between two consecutive gain settings propagation delay CL = 68 pF - - 160 - - 20 ns ns
HARMONICS; TAMB = 25 C HD2 second harmonic distortion fi = 15 MHz; at Vo(dif)(max); at gain control register: 00H 20H 3FH HD3 third harmonic distortion fi = 15 MHz; at Vo(dif)(max); at gain control register: 00H 20H 3FH tbf tbf - 50 50 50 - - - dB dB dB 40 40 - tbf tbf tbf - - - dB dB dB
1999 Sep 16
11
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with DPGA
SYMBOL NOISE Vn(o)(rms) output referred noise (RMS value) DPGA at G(max); Zi = 50 ; noise bandwidth = 15 MHz - tbf PARAMETER CONDITIONS MIN. TYP.
TDA8798
MAX.
UNIT
2
mVrms
ADC (without DPGA; fCLK = 100 MHz; from buffer input to digital output) ANALOG INPUTS (BUF1, BUF1N, BUF2 AND BUF2N) Vi(dif)(FS)(p-p) differential input voltage full-scale amplitude; (peak-to-peak value) common mode input voltage input current input resistance input capacitance at Vi(cm)(ADC) - 500 - mV
Vi(cm)(ADC) Ii(ADC) Ri(ADC) Ci(ADC) NLdc(i)
- - - - ramp input; without DPGA with DPGA at G(min) - -
tbf tbf 20 3
- - - -
V A k pF
STATIC LINEARITY DC integral non-linearity 1.0 3.0 tbf tbf LSB LSB
NLdc(dif)
DC differential non-linearity
ramp input; without DPGA with DPGA at G(min) - - 0.5 0.5 tbf tbf LSB LSB
DYNAMIC PERFORMANCE THD S/N BANDWIDTH B(-3dB)(ADC) ct VIL VIH IIH IIL VIL VIH IIH IIL ADC -3 dB analog bandwidth crosstalk between channels - - - 2.0 - -100 - 2.0 -5 -5 120 -40 - - - - - - - - - - 0.8 VDDD 100 - 0.8 VDDD +5 +5 MHz total harmonic distortion signal-to-noise ratio fi = 4.43 MHz without harmonics - - -55 -46 - - dB dB
CROSSTALK BETWEEN ADC1 AND ADC2 dB
CLOCK INPUTS: CLK1, CLK1N, CLK2 AND CLK2N; note 1 LOW-level clock input voltage HIGH-level clock input voltage HIGH-level clock input current LOW-level clock input current V V A A V V A A
DIGITAL CONTROL INPUTS (OE, TE, TEST, DPGAEN AND SR) LOW-level input voltage HIGH-level input voltage HIGH-level input current LOW-level input current
1999 Sep 16
12
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with DPGA
SYMBOL PARAMETER CONDITIONS - -20 MIN. - - TYP.
TDA8798
MAX.
UNIT
DIGITAL OUTPUTS (A0 TO A7 AND B0 TO B7) VOL VOH IOZ LOW-level output voltage HIGH-level output voltage IO = 1 mA IO = -1 mA 0.4 - +20 V V A VDDO - 0.4 V -
output current in 3-state mode VO > 0.4 V; VO < (VDDO - 0.4 V) maximum clock frequency clock pulse width LOW duration clock pulse width HIGH duration clock pulse rise time clock pulse fall time
ADC CLOCK TIMING fCLK(max) tW(CLKL) tW(CLKH) tr(CLK) tf(CLK) td(s)(D) td(Q) th(Q) 100 4.0 4.0 0.75 0.75 - SR HIGH SR LOW data output hold time SR HIGH SR LOW 3-STATE OUTPUT DELAY TIMES (see Fig.6) tdZH tdZL tdHZ tdLZ output delay enable at logic HIGH output delay enable at logic LOW output delay disable at logic HIGH output delay disable at logic LOW SR HIGH SR LOW SR HIGH SR LOW SR HIGH SR LOW SR HIGH SR LOW - - - - - - - - - at Vo(ref) - - - tbf tbf tbf tbf tbf tbf tbf tbf tbf tbf tbf tbf tbf tbf tbf tbf - 10 - 3 ns ns ns ns ns ns ns ns - - tbf tbf - - - 1 1 - 5.0 tbf 5.0 tbf - - - 2 2 MHz ns ns ns ns
DATA TIMING (see Fig.4); FCLK = 100 MHZ; CDPGAC = 10 PF data sampling delay time data output delay time tbf tbf tbf - - ns ns ns ns ns
ADC REFERENCE OUTPUTS (VREF1 AND VREF2) Vo(ref) Ro(ref) Io(ref)(max) Co(ref) ADC reference output voltage ADC reference output resistance ADC reference maximum output current ADC reference output capacitance 1.24 - 4.0 - V mA pF
1999 Sep 16
13
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with DPGA
SYMBOL PARAMETER CONDITIONS - at Vo(cm)(ref) at Vo(cm)(ref) - 0.2 V - - - MIN. TYP.
TDA8798
MAX.
UNIT
COMMON MODE REFERENCE OUTPUTS (VOREF1 AND VOREF2) Vo(ref) Ro(ref) Io(ref) Co(ref) reference output voltage reference output resistance reference maximum output current reference output capacitance VDDA - 0.42 V - 400 170 - - - 3 V A pF
Serial Interface DIGITAL INPUTS (SEN1, SEN2, SCLK, SDATA AND SMODE) VIL VIH IIH IIL fSCLK(max) tW(SCLKH) tW(SCLKL) tsu(SEN-SCLK) th(SEN-SCLK) LOW-level input voltage HIGH-level input voltage HIGH-level input current LOW-level input current 0 2.0 -5 -5 5 20 20 5 5 5 5 5 - - - 0 0 - - - - - - - - - 0.8 VDDD +5 +5 - - - - - - - - 5 V V A A MHz ns ns ns ns ns ns ns ns
GAIN CONTROL DATA TIMING (see Fig.4) maximum clock frequency clock pulse width HIGH clock pulse width LOW SEN to SCLK set-up time SEN to SCLK hold time
tsu(SDATA-SCLK) SDATA to SCLK set-up time th(SMODE-SCLK) SMODE to SCLK hold time th(SMODE-SEN) td(SEN-Q) SMODE to SEN hold time delay SEN rising edge to change gain control register value delay SCLK rising edge to change gain control register value
td(SCLK-Q)
-
-
5
ns
Note 1. Single-ended clock signal sources are allowed. The unused clock input is internally biased at the logical threshold (1.65 V for nominal supply conditions), and should be correctly decoupled.
1999 Sep 16
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parallel load mode
SMODE th(SMODE-SEN) SEN th(SMODE-SCLK) tsu(SEN-SCLK) SCLK t W(SCLKH) t W(SCLKL) tsu(SEN-SCLK) th(SEN-SCLK) 50% tsu(SDATA-SCLK)
Philips Semiconductors
Dual 8-bit, 100 Msps A/D converter with DPGA
handbook, full pagewidth
count-up/count-down mode
50%
tsu(SEN-SCLK)
50%
up = 1 down = 0 D5 D4 D3 D2 D1 D0 (LSB) td(SEN-Q)
up = 1 down = 0
15
SDATA (MSB) SI GAIN CONTROL REGISTER tst(G-G) DPGA OUTPUTS tPD
td(SCLK-Q) D5 D4 D3 D2 D1 D0 REG +/-1 REG +/-1
10% 90%
MGM865
Objective specification
TDA8798
Fig.4 Timing diagram of serial interface.
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with DPGA
TDA8798
handbook, full pagewidth
t W(CLKL) t W(CLKH) HIGH CLK sample N + 1 sample N + 2 50 % LOW sample N
Vi
td(s)(D) DATA A0 to A7 B0 to B7
th(Q) HIGH
DATA N-2
DATA N-1 td(Q)
DATA N
DATA N+1
MGM866
50 % LOW
Fig.5 Timing diagram for the ADC.
V handbook, full pagewidth DDO OE 0V tdHZ logic HIGH 90% data output tdLZ tdZL high impedance 50% logic LOW 10% VDDO A0 to A7 B0 to B7 3.3 k S1 10 pF TEST tdLZ tdZL tdHZ tdZH S1 VDDO VDDO GND GND
MGM868
50%
tdZH
50% high impedance
data output
TDA8798
OE
Fig.6 Timing diagram and test conditions of 3-state output delay time.
1999 Sep 16
16
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with DPGA
TEST AND APPLICATION INFORMATION
handbook, full pagewidth
TDA8798
3.3 V 100 nF(1) VSSA VSSD CLK2
3.3 V 100 nF(1) VSSD VSSD TE DPGAEN
3.3 V 100 nF(1) VSSO
VSSA VDDA4 BUF2N VSSA4 BUF2 100 nF
(2)
OE
SR
100 nF VSSD VDDD2 VSSD2 CLK2
VSSO VDDO2 50 VSSO2 49
SR 52
TE
64
63
62
61
60
59
58
57
56
55
54
DPGA2N DPGA2 68 pF(3) VSSA VSSA 3.3 V VIN2N VIN2 DPGAC2 Vref2 100 nF(1) V DDA2 100 nF(4) 100 nF(4) VIN2N VIN2 VSSA2 VSSA1 100 nF(4) VIN1 VIN1N 3.3 V 100 nF(1) VSSA VSSA 68 pF(3) 100 nF(4) VIN1 VIN1N VDDA1 Vref1
53
51
OE
(2)
TEST
100 nF
DPGAEN
CLK2N
Voref2
1 2 3 4 5 6 7 8
48 47 46 45 44 43 42 41
B7 B6 B5 B4 B3 B2 B1 B0 A0 A1 A2 A3 A4 A5 A6 A7
B7 B6 B5 B4 B3 B2 B1 B0 A0 A1 A2 A3 A4 A5 A6 A7
TDA8798HL
9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 28 29 30 31 17 18 19 32 VSSO1 VSSO 100 nF(1) VSSD 3.3 V 3.3 V 40 39 38 37 36 35 34 33
DPGAC1 DPGA1 DPGA1N
BUF1N
Voref1
VDDA3
VSSD1
VDDD1
SEN1 SEN1
BUF1
SMODE
(2)
(2)
SMODE
SEN2
SDATA
VSSA
VSSD
100 nF 100 nF(1) VSSD VSSA 3.3 V
100 nF(1)
SCLK
CLK1
VDDO1
VSSA3
CLK1
CLK1N
SEN2
SDATA
SCLK
100 nF
100 nF
VSSO
MGM867
Analog and digital supplies must be separate and decoupled. (1) Supply decoupling capacitor must be placed as close as possible to the chip's pin. Value may need changing depending on the external filter characteristics. (2) Capacitor may be replaced when an external filter is used with AC coupling. (3) Capacitor value may be changed to adjust settling time between DPGA gain changes. (4) Capacitor value may need changing depending on the high-pass cut-off frequency of the external filter.
Fig.7 Application diagram.
1999 Sep 16
17
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with DPGA
INTERNAL PIN CONFIGURATIONS
handbook, halfpage V handbook, halfpage V
TDA8798
DDA1
DDA2
VIN1 VIN1N
0.5 V 1 k
VIN2 VIN2N
0.5 V 1 k
VSSA1
MGM869
VSSA2
MGM870
Fig.8 DPGA1 analog input.
Fig.9 DPGA2 analog input.
handbook, V halfpage
DDA3
handbook, V halfpage
DDA4
Voref1 0.42 V
Voref2 0.42 V
BUF1 BUF1N
20 k
BUF2 BUF2N
20 k
VSSA3
MGM871
VSSA4
MGM872
Fig.10 ADC1 buffer input and Voref1 output.
Fig.11 ADC2 buffer input and Voref2 output.
handbook, halfpage V
DDD1
handbook, halfpage V
DDD2
CLK1
CLK2
CLK1N 20 k 1.4 V VSSD1
MGM873
CLK2N 20 k 1.4 V VSSD2
MGM874
Fig.12 ADC1 clock buffer input.
Fig.13 ADC2 clock buffer input.
1999 Sep 16
18
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with DPGA
TDA8798
handbook, halfpage
VDDA3 VDDA1 100
handbook, halfpage
VDDA4 VDDA2 100
DPGA1 DPGA1N
DPGA2 DPGA2N
VSSA1
MGM875 MGM876
VSSA2
Fig.14 DPGA1 buffer output.
Fig.15 DPGA2 buffer output.
handbook, halfpage
VDDD1
handbook, halfpage
VDDD2
SMODE SEN1 SEN2 SDATA SCLK VSSD1
MGM877
TE DPGAEN
VSSD2
MGM878
Fig.16 Serial Interface inputs.
Fig.17 TE and DPGAEN inputs.
handbook, halfpage handbook, halfpage V DDO2
VDDO1 OE
OE SR
A0N A0
VSSO2
MGM879 MGM880
VSSO1
Fig.18 OE and SR inputs.
Fig.19 ADC1 A0 to A7 outputs.
1999 Sep 16
19
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with DPGA
TDA8798
handbook, halfpage
VDDO2 OE VDDA3
B0N B0 1.24 V
Vref1
VSSA3 VSSO2
MGM881 FCE268
Fig.20 ADC2 B0 to B7 outputs.
Fig.21 Vref1 output.
VDDA4
Vref2
1.24 V VSSA4
FCE269
Fig.22 Vref2 output.
1999 Sep 16
20
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with DPGA
PACKAGE OUTLINE LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
TDA8798
SOT314-2
c
y X A 48 49 33 32 ZE
e E HE wM bp 64 1 pin 1 index 16 ZD bp D HD wM B vM B vM A 17 detail X L Lp A A2 A1 (A 3)
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.60 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7 0o
o
12.15 12.15 11.85 11.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT314-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-12-19 97-08-01
1999 Sep 16
21
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with DPGA
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
TDA8798
* For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1999 Sep 16
22
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with DPGA
Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable suitable(2) recommended(3)(4) recommended(5) suitable not not suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not
TDA8798
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
1999 Sep 16
23
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 68
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545004/25/02/pp24
Date of release: 1999
Sep 16
Document order number:
9397 750 05466

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